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 Packagers like Taiwan's Advanced Semiconductor Engineering Inc (ASE)
receive chips from manufacturers and prepare them for device
assemblers by, for instance, encasing them in metal and resin.
The advent of wearable devices, particularly Apple Inc's Apple Watch
and its dozens of chips, pushed packagers to devise innovative ways
of cramming ever-more communications, graphics and location chips
into the tiniest of spaces.
To serve this market, which researcher IDC expects to grow 173
percent to $17.1 billion in 2015, ASE and rivals like Taiwan's
Siliconware Precision Industries Co Ltd and Amkor Technology Inc of
the United States have come up with an assembly process known as
System-in-Package (SiP).
"SiP bundles a ton of components into one simple plug-n-play, almost
like a Lego block," said Taipei-based semiconductor analyst Randy
Abrams at Credit Suisse.
In SiP, the packager finds the optimal arrangement for multiple
chips, akin to solving a three-dimensional jigsaw. The tightly
packed formation allows for easier communication between chips,
yielding quicker, more energy-efficient devices.
"The SiP inside the Apple Watch was unprecedented," Vice President
Jim Morrison of analysis firm Chipworks told Reuters. Chipworks
found as many as 40 chips in the hermetically sealed pod, more than
double any other package it had seen before.
INTERNET OF THINGS
ASE aims to be a one-stop-shop for firms planning to stuff dozens of
chips into wearables such as wristbands, but also into home
appliances and even light bulbs as more and more goods go online - a
concept known as the Internet of Things (IoT).
"We spent up to seven years developing the design" of SiP, said ASE
Chief Operating Officer Tien Wu, who targets riches promised by an
IoT market IDC values at $1.7 trillion by 2020.
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ASE commands a leading 19 percent of the packaging market. It
supplies a large share of SiPs for the Apple Watch as well as for
the fingerprint sensors in Apple's iPhones, analysts said.
It booked revenue growth of 19 percent in January-June in part due
to SiP, and forecasts SiP business to double to 20 percent of
revenue in 2015. But with costs of SiP higher than those of
conventional chip packaging, profit margins may narrow. First-half
net profit fell 5.1 percent, ASE said on Thursday.
Analyst Carlos Peng at Fubon Securities said ASE's gross margin on
the Apple Watch SiP is 7 percent to 8 percent lower than the firm's
overall 20 percent margin booked last year.
"In an economy of scale it's still money-making," Peng said.
But SiP is not the smallest solution. A costlier approach is
System-on-Chip (SoC) in which a single chip performs multiple
functions. Though the technologically more complex SoCs are capable
of fewer functions, they could draw device makers away from SiPs if
the cost of incorporating functions declines.
Packagers may then lose out as the financial benefits of SoCs would
go to SoC designers such as Qualcomm Inc and MediaTek Inc. For now,
however, SiPs are cheaper and easier, analysts said.
"We're building a new business model" with SiP, said ASE Chief
Financial Officer Joseph Tung.
(Reporting by Michael Gold; Editing by Christopher Cushing)
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